Performance goals of processors increase in every generation and progressively more sophisticated architectures are required to implement their complex functions. Advanced architectures require long pipelines which increase the number of latches used to interface pipeline stages. These latches consume considerable amounts of power and area.
Domino circuits increase the performance of logic circuits by precharging a series of logic gates during a first clock phase, or precharge phase, and evaluating the intended logic function during the next clock phase, or evaluation phase. Domino circuits have three sources of overhead which reduce performance: latches, clock skew, and the inability to borrow time across clock boundaries. Opportunistic time borrowing (OTB) domino circuits improve performance by eliminating these three sources of overhead for interfacing two phases of domino circuits. A full description of OTB domino circuits can be found in U.S. Pat. No. 5,517,136 issued May 14, 1996. However, OTB domino is not applicable to interfacing static logic to domino logic. Interfacing static logic to domino logic is expensive in terms of time, power consumption, and area. One of the constraints of domino logic is that there can be no false transition or valid high to low transition at its input while the domino logic operates. Such a high to low transition may cause an erroneous output. Glitches in the output of the static logic block may accidentally trigger domino circuits in this way. Therefore, in the prior art, a latch is required to hold a stable input from the static logic to the domino logic.
FIG. 1A illustrates a block diagram of a prior art interface between a static logic block 110 and a domino evaluation tree 130. The domino evaluation tree 130 is a logic block made of N-type MOSFET transistors which may evaluate one of a number of functions. For example, the domino evaluation tree 130 may implement a NAND or NOR function. The method of implementing such functions in NMOS is well known in the art. The output of the static logic block 110 is latched by the latch 120 in order to provide a stable input to the domino evaluation tree 130.
FIG. 1A shows one input, IN, from the static logic block 110 interfaced to the domino evaluation tree 130 by latch 120. However, the domino evaluation tree 130 may have more than one input from a static logic interfaced in a similarly. The domino gate 175 is clocked by the complimentary clock signal, CLK# 182. The domino gate 175 includes the domino evaluation tree 130, an NMOS evaluation transistor 140, a PMOS precharge transistor 150, and a PMOS sustainer 160. Domino evaluation tree 130 is connected to the NMOS evaluation transistor 140, which only allows evaluation while CLK# signal 182 is high. The domino evaluation tree 130 is also connected to the PMOS precharge transistor 150, which pulls the OUT signal 190 high during the precharge phase, while CLK# signal 182 is low.
Further, the output of the domino evaluation tree 130 is coupled to a PMOS sustainer 160. The PMOS sustainer 160 consists of an inverter 166, with the output of the inverter 166 coupled to the gate of a PMOS device 163. This PMOS device 163 is coupled between the operating supply and the output of the domino evaluation tree 130. The function of the PMOS sustainer 160 is to keep the output high--to keep it from floating--if the domino evaluation tree does not pull it low. Finally, the output of the domino gate 175 is an input to the Phase II logic block 170.
FIG. 1B represents the timing diagram of the circuit illustrated in FIG. 1A. The IN signal 185 is input to the latch 120 and the output of the latch 120 is the IN(L) signal 187. The IN signal 185 becomes valid at least t.sub.s prior to the end of Phase I. The time t.sub.s is the setup time of the latch 120. The IN(L) signal 187 must become valid before the start of Phase II in order for the IN(L) signal 187 to be stable when the domino evaluation tree 130 operates. The output signal, OUT 190, is the output of the domino gate 175 and becomes valid during Phase II.
The latch 120 performs no logic, but only holds a stable input for the domino gate 175 during Phase II. The latch 120 adds the propagation delay through the latch or the setup time of the latch to the critical path. In addition, the latch 120 increases the area and power consumption of the circuit.
Thus it can be seen that an improved interface from static to domino logic, which eliminates the need for a latch, is desirable.